The present invention relates generally to cache memories, and, more particularly, to validation of locking and unlocking of a cache memory.
A cache memory is a type of memory in a processing system for temporarily storing data or instructions that are likely to be used again. In many modern processing systems, the cache memory is classified into different levels of hierarchy based on its size and the latency period for fetching requested data, such as L1 (level 1), L2, L3, etc. The processing system starts searching for the requested data or instruction in the first level cache (L1) onwards. As the level of hierarchy increases, the time required for fetching the requested data or instruction also increases, thereby increasing the latency.
Typically, the requested data or instruction is stored in cache lines of the cache memory. Each cache line maps to a particular block of addresses in the memory of the main processing system. Since the number of cache lines is less than the number of blocks of addresses, there are a few methods for mapping different blocks of addresses to the cache lines, such as direct mapping, associative mapping, and set-associative mapping. In direct mapping, each block of addresses of the main processing system memory maps to only one cache line in the cache memory. In associative mapping, a block of addresses from the main processing system memory can map to any cache line of the cache memory. In set-associative mapping, the cache memory is divided into sets of cache lines, with each set having a fixed number of cache lines. A block of addresses from the main processing system memory can map to any cache line in a given set determined by that block's address. Once a block of addresses is successfully mapped to a cache line, the processing system can easily fetch the data or instruction from the cache memory.
Sometimes it is possible for the data or instruction stored in the cache memory to be overwritten in duration of time-to-live (TTL) interval. To avoid such errors, cache locking is enabled, which ensures protection against erroneous handling of the cache memory. A cache hit within a locked cache memory is served in a similar manner as that served by an unlocked cache memory, whereas a cache miss in the locked cache memory is considered as a cache-inhibited access. The cache memory can be completely locked or partially locked (‘way locking’) when the data or instruction size is small as compared to the size of the cache memory. In way locking, only a portion of the cache memory is locked by locking ways of a determined set of the cache memory.
Since cache locking is an important feature, there is a need to validate this feature on a chip during post-silicon validation. There are different ways to validate the cache locking feature. FIG. 1 is a flow chart illustrating a conventional method for validating the cache locking and unlocking features. At step 102, a processor that is in communication with the cache memory is set to operate in a supervisor mode. At step 104, the targeted cache memory is enabled. At step 106, addresses corresponding to cache lines of the targeted cache memory are selected for validating the locking and unlocking features. At step 108, the locking and unlocking of each selected address is executed. At step 110, a check is performed to determine if locking and unlocking of each selected address was successful. If the locking and unlocking of each selected address was not successful, at step 112, a FAIL status signal is generated. Thereafter, steps 102-108 are repeated. On the other hand, if the locking and unlocking of each selected address is completed, at step 114, the locking and unlocking feature of the cache memory is validated and a PASS status signal is generated.
However, the above-mentioned method for validating the locking and unlocking features has several drawbacks. It validates the correctness of the locking feature for only a fixed number of selected addresses, and does not randomly validate the locking and unlocking feature by performing back to back locking and unlocking of the cache lines. Another feature of the cache memory, referred to as the ‘lock-flash clear’ feature, in which all the selected addresses are unlocked simultaneously, cannot be validated by this method. Also, this method does not extend to the different hierarchies of the cache memories, such as L1, L2, and L3.
Therefore, it would be advantageous to have a system and method for validating the locking and unlocking features of the cache memory that randomly selects the addresses based on the cache memory configuration and performs back-to-back locking and unlocking operations on the selected addresses, that can be implemented for all levels of cache hierarchy, that additionally validates the lock-flash clear feature, and that generally overcomes the above-mentioned problems of the existing method for validating the locking and unlocking features of a cache memory.